1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems having a processor core with a register bank executing instructions of a first instruction set being used in conjunction with an instruction translator operable to translate instructions of a second instruction set into instructions of the first instruction set.
2. Description of the Prior Art
It is known to provide data processing systems supporting multiple instruction sets. An example of such systems are the Thumb enabled processors produced by ARM Limited of Cambridge, England that may execute both 16-bit Thumb instructions and 32-bit ARM instructions. Both the Thumb instructions and the ARM instructions execute operations (such as mathematical manipulations, loads, stores etc) upon operands stored within registers of the processor core specified by register fields within the instructions. Considerable effort is expended in developing compilers that are able to efficiently use the register resources of the processor core to produce instruction streams that execute rapidly.
Another class of instruction sets are those that use a stack approach to storing and manipulating the operands upon which they act. The stack within such a system may store a sequence of operand values which are placed into the stack in a particular order and then removed from the stack in the reverse of that order. Thus, the last operand to be placed into the stack will also typically be the first operand to be removed from the stack. Stack based processors may provide a block of storage elements to which stack operands may be written and from which stack operands may be read in conjunction with a stack pointer which indicates the current “top” position within the stack. The stack pointer specifies a reference point within the stack memory which is the latest stack operand to be stored into the stack and from which other accesses to the stack may be referenced. Considerable effort is also expended in producing compilers that are able to efficiently utilise the stack hardware resources within such stack based processor systems.
A specific example of a stack based instruction set is the Java Virtual Machine instruction set as specified by Sun Microsystems Inc. The Java programming language seeks to provide an environment in which computer software written in Java can be executed upon many different processing hardware platforms without having to alter the Java software.
It is a constant aim within data processing systems that they should be able to execute the computer software controlling them as rapidly as possible. Measures that can increase the speed with which computer software may be executed are strongly desirable.
Examples of known systems for translation between instruction sets and other background information may be found in the following: U.S. Pat. No. 5,805,895; U.S. Pat. No. 3,955,180; U.S. Pat. No. 5,970,242; U.S. Pat. No. 5,619,665; U.S. Pat. No. 5,826,089; U.S. Pat. No. 5,925,123; U.S. Pat. No. 5875,336; U.S. Pat. No. 5,937,193; U.S. Pat. No. 5,953,520; U.S. Pat. No. 6,021,469; U.S. Pat. No. 5,568,646; U.S. Pat. No. 5,758,115; U.S. Pat. No. 5,367,685; IBM Technical Disclosure Bulletin, March 1988, pp308–309, “System/370 Emulator Assist Processor For a Reduced Instruction Set Computer”; IBM Technical Disclosure Bulletin, July 1986, pp548–549, “Full Function Series/1 Instruction Set Emulator”; IBM Technical Disclosure Bulletin, March 1994, pp605–606, “Real-Time CISC Architecture HW Emulator On A RISC Processor”; IBM Technical Disclosure Bulletin, March 1998, p272, “Performance Improvement Using An EMULATION Control Block”; IBM Technical Disclosure Bulletin, January 1995, pp537–540, “Fast Instruction Decode For Code Emulation on Reduced Instruction Set Computer/Cycles Systems”; IBM Technical Disclosure Bulletin, February 1993, pp231–234, “High Performance Dual Architecture Processor”; IBM Technical Disclosure Bulletin, August 1989, pp40–43, “System/370 I/O Channel Program Channel Command Word Prefetch”; IBM Technical Disclosure Bulletin, June 1985, pp305–306, “Fully Microcode-Controlled Emulation Architecture”; IBM Technical Disclosure Bulletin, March 1972, pp3074–3076, “Op Code and Status Handling For Emulation”; IBM Technical Disclosure Bulletin, August 1982, pp954–956, “On-Chip Microcoding of a Microprocessor With Most Frequently Used Instructions of Large System and Primitives Suitable for Coding Remaining Instructions”; IBM Technical Disclosure Bulletin, April 1983, pp5576–5577, “Emulation Instruction”; the book ARM System Architecture by S Furber; the book Computer Architecture: A Quantitative Approach by Hennessy and Patterson; and the book The Java Virtual Machine Specification by Tim Lindholm and Frank Yellin 1st and 2nd Editions.